RAYTHEON’S THREE-DIMENSIONAL HETEROGENEOUS INTEGRATION (3DHI) ELECTRONICS TECHNOLOGY

Defense applications continue to demand higher performance and efficiency from electronics while minimizing size, weight, and power (SWaP) across an increasing range of radio frequency (RF) and optical frequencies. In meeting these needs, traditional or homogeneous Silicon (Si) and III-V material based solutions as well as other microelectronic solutions face inherent technology performance limits along with the SWaP limitations of traditional two-dimensional (2D) and 2.5D1 fabrication methods.

The three-dimensional (3D) and flexible integration of multiple heterogeneous device technologies can help address these limitations in future systems. The 3D heterogeneous integration (3DHI) of high power and efficiency Gallium Nitride (GaN) power amplifiers (PAs) with functionally dense Si CMOS (complementary metal-oxide-semiconductor) logic will create a new class of compact, digitally enhanced RF integrated circuits (ICs) that will revolutionize radar and multifunction systems. Creating cost-effective 3DHI ICs is both highly desirable and necessary for the realization of advanced systems capabilities.  

Raytheon’s approach to 3DHI takes advantage of companywide design and fabrication capabilities in advanced microelectronics as well as existing and emerging 3D commercial technologies, such as wafer bonding, interposers and 3D fabrication techniques. This cost-effective strategy of using both internal and external technology sources builds on Raytheon’s expertise in the design of RF circuits and Microelectromechanical Systems (MEMS) devices; fabrication of Focal Plane Arrays (FPAs) in 3D wafer bonded stacks; and assembly of electronic components and advanced packaging. Joint engineering design efforts are focused on creating 3D wafer-scale packages that can house specially designed 3D GaN Monolithic Microwave Integrated Circuits (MMICs) integrated directly into the package, stacks of 2D MMICs or more traditional 2D ICs from external sources. With Raytheon’s 3D wafer bonding capabilities, these wafers, which are already heterogeneous, can then be used to create wafer-level microelectronic systems. By combining this wafer bonding technology with reconstituted wafers to create 3D wafer-level packages, Raytheon is developing an overall 3DHI process that is functionally dense, flexible, and high performance, with potential to significantly improve the effectiveness of future defense electronic systems.

3D Wafer Stacks

Figure 1: Scanning Electron Microscope cross section of a focal plane array (FPA) made with 3D wafer bonding with the multilevel Readout Integrated Circuit (ROIC) on the bottom and the Detector on top. This proven wafer bonding technology is foundational in Raytheon’s approach to 3D heterogeneous integration (3DHI).5

Raytheon’s 3DHI technology takes advantage of the successful fabrication of FPAs in 3D wafer bonded stacks, which has been refined into a Direct Bond Hybridization (DBH) process. DBH is used for the production of FPAs, in which very large format photon detector arrays are bonded directly onto Si readout ICs at the wafer-level. An example of this process, used in a variety of formats currently in production, is shown in Figure 1.

The DBH wafer bonding technology is being extended with new design rules, which enable the development of highly integrated 3D systems.2,3,4 The changes include an increase in interconnect flexibility, increased thickness of metal layers and the ability to use both high resistivity Si wafers or low-loss fused silica as substrate materials. These enhancements allow for increased flexibility in the processing and the implementation of very low-loss RF transmission lines in all three axes.

Design and Heterogeneous Integration Approach

To address the challenges and opportunities of 3DHI for RF and mixed signal applications, Raytheon designers are creating 3D HIMMICs (Heterogeneously Integrated Monolithic Microwave Integrated Circuits) and 3D wafer-scale packages that can house specially designed 3D GaN MMICs integrated directly into the package, stacks of GaN 2D MMICs, or traditional 2D ICs from external sources. A key element of the underlying technology is the integration of high performance compound semiconductor RF devices. One example of this is the integration of GaN High Electron Mobility Transistors (HEMTs) with silicon-based circuits, such as logic and control circuits, to create “intelligent” or digitally enhanced RF ICs.6 Figure 2 is an example of a 200 mm diameter GaN-on-Si wafer bonded to, and interconnected with, a 200 mm diameter Si CMOS wafer to create wafer-scale RF modules or, when diced, individual chips or HIMMICs. Raytheon has achieved both very high vertical interconnect yield and good RF electrical performance with this integration approach. The microwave and millimeter wave GaN transistors integrated into the HIMMIC have RF characteristics similar to the native GaN transistors. The GaN-Si CMOS HIMMIC technology allows for the integration of three different RF and digital functions previously implemented separately in three different semiconductor technologies. Now these functions are integrated as part of an RF transceiver on a single chip with reduced X-Y foot print and greater RF performance (higher power, higher dynamic range, lower noise figure) to enhance the performance and capabilities of next generation multifunction systems for radar, communications and electronic warfare applications.

Figure 2: A Silicon (Si) CMOS (Complementary metal–oxide–semiconductor) wafer oxide bonded to a Gallium Nitride (GaN) on Si wafer. This HIMMIC technology builds on many years of circuit design expertise and brings together two key technologies — GaN and Si CMOS — at the wafer scale.

Another area of 3DHI development is Raytheon Advanced Invariant Die, or RAID (Figure 3), which is a multitier chip scale package capable of incorporating multiple semiconductor device types and orientations.7,8 The RAID package is manufactured using standard semiconductor fabrication techniques.  

Figure 3: An example schematic of a multi-tier RAID package (left bottom) and a Scanning Electron Microscope (SEM) image of a Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) mounted inside a RAID package (right top).

The RAID technology uses Silicon Carbide (SiC) as the base substrate material for its tiers, ensuring a high degree of heat spreading throughout the stack and providing a lower coefficient of thermal expansion among the vertical tiers. Known-good9 MMICs can then be used for wafer-scale manufacturing, with this technique allowing high density packaging benefits for the overall system. 

Incorporating MMICs in a small cavity has potential negative consequences, including undesirable resonances across the band of RF operation. In order to suppress these resonances, cutouts are selectively placed throughout the tier stack and topped-off with an electronic bandgap (EBG) material lid, which presents a similar impedance to the MMIC as experienced in much larger conventional package assemblies. This allows the 3DHI stack to be approximately 100 times thinner than comparable microwave assemblies, enabling the stack to be incorporated into the wafer-scale processing and bonding processes. RAID is based on established RF and MEMS design techniques and is made in Raytheon’s foundry using proven semiconductor fabrication processes.

The RAID stack can incorporate multiple MMICs, in either the X- or Y-direction or stacked on top of each other in the Z-direction. The interconnects traverse between the MMICs within the tiers and provide signal, control and power lines that can be terminated on the top or bottom of the package. The RAID package can also provide interconnect tabs on each side of the tiers, much like beamleads for integration to the wafer-scale assembly. The above design and fabrication capabilities enable multiple degrees of freedom in the overall system integration approach, enhancing the functional density by incorporating the best available technologies in a single wafer-scale package. The RAID package was demonstrated at 94 GHz using a GaN power amplifier MMIC packaged in a six-tier vertical stack highlighting the high frequency quality factors of this approach.10 

Flexible and High Performing Integrated Systems

The final element of Raytheon 3DHI is the integration of all the constituent pieces and technologies to provide ultimate design flexibility and maximum performance. This requires combining the wafer bonding, HIMMIC and RAID technologies. The wafer bonding and HIMMIC processes are readily compatible and can be directly integrated to make 3D wafer stacks of heterogeneous devices, which are then used in wafer-scale electronics or diced into 3D modules. 

In order to extend the use of wafer-scale stacking to individual chips and RAID packages, Raytheon is developing techniques to embed chips of different technologies into 200 mm diameter wafers. This structure is referred to as Chip-in-Wafer (CiW) and is essentially a variation of the more commonly referred to reconstituted wafer (RW). Shown in Figure 4, CiW consists of a base wafer, a spacer, cavity or waffle wafer, and a lid wafer, where each wafer contains vertical (3D) and horizontal (2D) interconnects. The lid and base wafers can be either passive (interconnects only) or active (containing Si circuits) and can be thought of as “interposers,” or signal redistribution layers, a substrate technology commonly used to create 2.5D multichip assemblies.

Figure 4: Raytheon’s Chip-In-Wafer (CIW) Technology. A Schematic cross section of heterogeneous chips integrated into a silicon (Si) CiW (top) and an Image of an initial prototype 200 mm diameter CiW (right). This CiW technology is a variation of a reconstituted wafer (RW) and allows for the incorporation of different integrated circuit (IC) device types into Si wafers, where it can then be used in wafer-scale processes such as 3D wafer bonding.

Using the CiW/RW approach with RAID brings together all aspects of the 3DHI technology to maximize design flexibility and performance. The integration of the tiers and encapsulation of known-good MMICs builds toward a larger wafer-scale and 3DHI integration with associated interconnects, thermal management, and the required electrical-thermal-mechanical co-design (Figure 5).   

Figure 5: Conceptual illustration of Raytheon Advanced Invariant Die (RAID), allowing known-good-MMICs to be integrated at wafer-scale for 3DHI integration of next generation systems.

Conclusion

Building an effective defense against today’s emerging threats demands future DoD electronics to have both greater capability and higher performance in a reduced form factor, particularly as systems migrate to higher frequency bands and more compact sizes. Raytheon is helping customers meet this need by developing a range of 3D packaging technologies to provide multiple options for integrating semiconductors of differing materials and type for RF, mixed signal, optical, and digital applications. These technologies, including advanced 3D wafer bonding, GaN-Si CMOS HIMMICs, RAID, and CiW, form the foundation of Raytheon’s 3DHI approach and build on core competencies in circuit design, assembly and packaging. Raytheon’s 3DHI strategy is flexible and promotes high performance in order to provide the advanced capabilities required by future electronic systems for the most demanding of customer missions.  

— Thomas E. Kazior
— Jeffrey LaRoche,
— Hooman Kazemi
— John Drab
— Jason G. Milne,
— Joseph J. Maure
— Avram Bar-Cohen

 

2.5D refers to a three-dimensional (3D) surface comprised of multiple flat (or planar) surfaces at varying elevations, having no angled surfaces or undercuts.
S. Kilcoyne, B. Kean, J. Cantrell, J. Fierro, L. Meier, S. DeWalt, C. Hewett, J. Wyles, J. Drab, G. Grama, G. Paloczi, J. Vampola, K. Brown, “Advancements in Large Formal SiPiN Hybrid Focal Plane Technology.” Proc. SPIE 9219 Infrared Remote Sensing and Instrumentation XXII, Sept 2014.
J. Drab, “Multilevel Wafer Stacking for 3D Circuit Integration.” Raytheon Technology Today, No. 1, 2015.
J. Drab, J.G. Milne, “Die Encapsulation in Oxide Bonded Wafer Stack.” US Patent No. 10,242,967.
J. Drab, “Multilevel Wafer Stacking for 3D Circuit Integration.” Raytheon Technology Today, No. 1, 2015.
T.E. Kazior, J. LaRoche, “Wafer Scale Integration of GaN with Si CMOS for RF Applications.” Plenary Presentation, International Workshop on Nitride Semiconductors (IWN2016), Oct 2016.
H. Kazemi, M. J. Rosker, T. E. Kazior, S. A. O’Connor, E. Elswick, “A Reconstituted Wafer Structure.” US Patent Publication 2019/0165108, Pending, 2017.
H. Kazemi, S. A. O’Connor, M. J. Rosker, J. J. Maurer, T.E. Kazior, J.B. Langille, W. J. Davis, J. Kotce, J. C. Moran, “Millimeter-wave Wafer Scale Packaging using an Advanced Invariant Die Architecture.” GOMACTech, March 2019.
Known-good refers to individual chips that have been screened and meet certain electrical performance criteria. These MMICs are chosen to be used in the 3D and/or heterogeneous integration process, greatly reducing the possibility of discovering a problem or poor yield in testing of the final 3D assembly.
10 H. Kazemi, S. A. O’Connor, M. J. Rosker, J. J. Maurer, T.E. Kazior, J.B. Langille, W. J. Davis, J. Kotce, J. C. Moran, “Millimeter-wave Wafer Scale Packaging using an Advanced Invariant Die Architecture.” GOMACTech, March 2019.