COSMOS: A Path to Next-Generation,
High-Performance, Mixed Signal Circuits
Raytheon's research in Compound Semiconductor Materials on Silicon (COSMOS) will enable a new class of high-performance mixed-signal integrated circuits (ICs) that enhance the capabilities of U.S. Department of Defense (DoD) systems through direct monolithic integration of compound semiconductors — such as gallium arsenide (GaAs) and indium phosphide (InP) — and silicon (Si) CMOS on a common, low-cost silicon substrate. Using COSMOS technology, Raytheon is designing and fabricating high-speed, high dynamic range, low-power dissipation converter circuits (analog to digital converters, or ADCs, and digital to analog converters, or DACs) with performance that cannot be achieved with today's technology.
The future of integrated circuits will include the integration of high-performance III-V electronic and/or opto-electronic devices with standard Si CMOS. While traditional hybrid approaches — such as wire bonded or flip-chip multi-chip assemblies (see Figure 1) — may provide short-term solutions, the variability, losses and size of the interconnects and the limitation in the placement of III-V devices relative to CMOS transistors limit the performance, utility, size and cost benefits of these approaches. A more attractive approach is the direct integration of Si CMOS and III-V devices on a common silicon substrate (Figure 1, right). In this way, circuit performance can be optimized by the strategic placement of high-performance III-V devices adjacent to Si CMOS transistors and cells, and the devices and subcircuits can be interconnected using standard semiconductor on-wafer interconnect processes.
Integrating III-V devices on silicon wafers is not new. For example, in the 1980s and 1990s, there was considerable, although unsuccessful, effort to “grow” GaAs devices on silicon wafers. So what is new this time?
Overcoming Technical Challenges
To address the many technical challenges associated with the direct integration of silicon CMOS and III-V devices on the same wafer, Raytheon assembled a team of internationally recognized experts in the fields of materials/substrate engineering and advanced semiconductor devices.
The first challenge was the creation of a substrate that is compatible with both silicon and III-V device materials and fabrication processes. To address this challenge, Raytheon worked with Eugene Fitzgerald of the Materials Science Department of the Massachusetts Institute of Technology (MIT) and Paradigm Research LLC, a world-renowned expert in semiconductor substrate engineering. To facilitate integration of III-V devices with silicon CMOS, Fitzgerald developed SOLES — silicon on lattice engineered substrates. SOLES wafers, a variation of silicon on insulator (SOI) substrates commonly used for the fabrication of silicon ICs, allow for the fabrication of silicon devices on the silicon surfaces and the direct growth and fabrication of compound semiconductor material (GaAs, InP) devices (high electron mobility transistors, or HEMTs, and heterojunction bipolar transistors, or HBTs) on a buried template layer (Figure 2). To a silicon wafer fab, SOLES look like a standard silicon or SOI wafer. The SOLES wafer technology was transitioned from MIT to production at Soitec in France, the world’s leading supplier of SOI wafers.
The second challenge was demonstrating that the silicon CMOS fabricated on SOLES performed the same as silicon CMOS on native silicon substrates. For this task, the team selected Raytheon’s 100mm silicon fab at Raytheon Systems Limited (RSL) in Glenrothes, Scotland. RSL successfully modified its 1.2mm production silicon CMOS process for compatibility with SOLES with no discernable change in transistor properties. To further drive cost and performance the process is being transitioned to 200mm diameter wafers and 180nm CMOS at SVTC in San Jose, Calif.
The third challenge was the selective growth of III-V devices on SOLES. Raytheon’s Advanced Semiconductor Material group, leaders in advanced III-V epitaxial growth, teamed with IQE in Bethlehem, Pa., the world’s leading supplier of III-V epitaxial material, to successfully demonstrate the growth of both InP HBT and GaAs pHEMT epitaxial material on SOLES. Key to this success was Raytheon’s and IQE’s pioneering work in metamorphic buffer layer technology, which enables the growth of high-quality semiconductor materials on dissimilar substrates.
The final challenge was the fabrication of high-performance compound semiconductor devices on SOLES and the interconnection of these devices with the silicon CMOS transistors. Here the team has focused on two complementary device technologies — InP HBTs for mixed signal applications and GaAs pHEMTs for RF applications.
For the integration of InP HBTs, the team leveraged Teledyne Scientific’s (Thousand Oaks, Calif.) expertise in InP HBT transistors and circuits developed under DARPA’s TFAST program to fabricate InP directly adjacent to Si CMOS transistors (Figure 3). The InP HBTs on SOLES exhibited performance that was comparable to InP HBTs fabricated on native InP substrates. Teledyne’s multilayer interconnect process, developed for InP mixed-signal circuits, was adapted for the creation of heterogeneous interconnects between InP HBTs and silicon CMOS with nearly 100 percent yield for InP HBT — silicon CMOS spacing as small as 2.5mm. The resulting device structure and fabrication process are analogous to a SiGe BiCMOS process where SiGe HBTs are replaced with an InP HBTs, but with a significant performance advantage due to the superior speed, gain and high-frequency performance, and higher operating voltage of InP HBTs.
Companion efforts underway at Raytheon’s MMIC foundry in Andover, Mass., have demonstrated GaAs pHEMTs on SOLES, with performance comparable to GaAs pHEMTs fabricated on native GaAs substrates
To demonstrate the viability of the COSMOS technology, the team successfully designed and fabricated a high-speed differential amplifier, which consisted of silicon CMOS current sources and an InP HBT differential pair (Figure 4). The complete circuit (differential amplifier with bias circuit and output buffer) contained over 100 heterogeneously integrated InP HBTs and silicon CMOS transistors. The circuit met all of the DARPA COSMOS Phase 1 Go/No-Go Milestones with first pass design success. This circuit is a building block for a low power dissipation (1.6W), high resolution (13 bit, greater than 78 dB spur free dynamic range digital-to-analog converter (DAC) currently being fabricated (Figure 5). The DAC, with its on-chip calibration circuitry contains over 6,000 heterogeneously integrated InP HBT and silicon CMOS transistors.
Addressing Next Steps
The COSMOS Phase 2 DAC is a building block for other types of high-speed, high dynamic range, low power dissipation converter circuits, including ADCs and direct digital synthesizers (DDS). The next step is to integrate these mixed-signal converter circuits with radio frequency transistors (HEMTs and HBTs) to enable single chip digital transceivers and dynamically reconfigurable circuits as well as compact circuit elements for low-cost panel arrays.
The new class of high-performance mixed-signal circuits enabled by the COSMOS technology will provide unprecedented performance, and size advantage to current and future RF systems, including: compact, high dynamic range radars; broadband communication systems; multi-beam communications for comm-on-the-move; high-resolution synthetic aperture radars (SAR) and inverse SAR; data links; active missile seekers; active self-protect systems; and multifunction unmanned air vehicle sensors.
While the circuit results presented here are for InP HBTs directly integrated onto the silicon substrate, the approach is equally applicable to other III-V electronic (e.g., GaAs pHEMTs or MHEMTs, GaN HEMTs) and opto-electronic (e.g., photodiodes, lasers - VSCLS) devices and opens the door to a new class of highly integrated, high-performance, mixed-signal circuits. These circuits will enhance the capabilities of existing DoD systems, enable new system architectures, and facilitate proliferation of low-cost sensors and active electronically scanned arrays for a wide range of DoD and U.S. Department of Homeland Security applications.
Thomas E Kazior
This work is supported in part by the DARPA
COSMOS Program (Contract Number N00014-
07-C-0629). The author would like to thank Mark
Rosker (DARPA) and Harry Dietrich (ONR).