Multilevel Wafer Stacking for 3D Circuit Integration
Three-dimensional (3D) integration of advanced silicon and radio frequency (RF) devices enables simpler and more reliable systems at a significantly lower cost. Raytheon offers a suite of available wafer level packaging technologies and processes in this area, including:
- Wafer-to-wafer bonding of silicon wafers with electrical interconnection.
- Fine pitch interconnection between bonded wafers using direct bond hybridization (DBH) (3 micron [µµm] interconnect on 6 µm pitch).
- Integration of DBH with through-wafer via technologies to produce advanced 3D silicon devices.
- Wafer-to-wafer bonding for 200 millimeter (mm) low loss fused silica and silicon structures.
- Processing of dimensions appropriate for high frequency 3D devices.
- High reliability bump bonding.
- Die-to-wafer bonding for tiles and other large die with fine pitch interconnect.
By maturing and leveraging these technologies and processes into manufacturing capabilities, Raytheon can supply a wide portfolio of programs with more reliable and lower cost hardware than is available using standard twodimensional (2D) approaches.
For many applications, the preferred approach to connecting the wafers is the DBH process. With DBH, the wafers are bonded using a lowtemperature hydrophilic oxide bond and the electrical interconnection is formed by metal posts that are planarized to the oxide surface. Figure 1 is an example cross-section from a scanning electron microscope (SEM) showing a DBH-bonded Si:PiN (silicon P-intrinsic-N) detector array stacked on a complementary metal oxide semiconductor (CMOS) readout integrated circuit (ROIC).
Although the process used to produce this appears quite simple and elegant, it has many subtleties. The interconnect posts are formed on the two wafers by electroplating on a seed metal layer through a plating mold made of patterned photoresist. Once the posts are plated, the photoresist and plating seed layers are removed and the interconnect posts are buried in the bonding oxide layer. For high frequency devices, a thicker seed layer is utilized that can be used to form low-loss transmission lines. This structure is buried in silicon dioxide (SiO2) bonding oxide which is then polished using a chemical-mechanical planarization (CMP) process to reveal the interconnect posts and planarize them with the oxide surface. For a good bond with effective interconnect, the surface must be very smooth and the interconnect plugs must be extremely planar. An atomic force microscope is used to perform metrology since nanometer scale tolerances are required. The CMP polishing process is significantly more difficult with 20 µm diameter posts than it is with the smaller 3 µm posts. Once the surfaces are planar, a combination of plasma and wet surface preparations are performed to achieve a good surface energy, after which the two wafers are very carefully aligned and brought into contact. Figure 2 shows the EV Group (EVG) wafer bond cluster tool used for final surface preparation, cleaning, alignment and bonding.
If the surfaces are very smooth and have the correct surface energy, they will grab and pull together. Once bonded, the wafers are checked for voids in the interface using an acoustic microscope. Raytheon Vision Systems has performed extensive work to increase the strength of the bond, as measured by the bond energy shown in Figure 3, and improve yield.
Alignment is verified using an infrared (IR) microscope and is approximately 1–1.5 µm across the 200 mm bond length for processed silicon wafer pairs. Figure 4 shows acoustic microscope images from a recent build of various format 8 µm pitch Si:PiN focal plane array (FPA) builds. These sonoscans show very few voids, which appear as white circles. In these images, the only voids that are apparent are over the bond pads and test structures around the perimeter of the wafer pairs as well as in the edge bead exclusion area.
The final step, if everything measures within the established process parameters, is to anneal the parts. During this anneal, the oxide bond energy rapidly increases as the oxide starts to form covalent bonds at the interface. Concurrently, the difference in coefficient of thermal expansion between the bonding oxide and the metal interconnect posts creates enough force to break through the native oxide on the interconnect posts and form an electrical connection.
Typical interconnect operability for this process is greater than 0.9999. The completed structure becomes a solid block of material that has no known fatigue issues due to stresses from packaging or temperature cycling. As part of the qualification process, sample daisy chain test structures were subjected to a series of tests ranging from hundreds of thermal shock cycles (room temperature to liquid nitrogen) to JEDEC1 temperature cycle testing. Sensor chip assemblies (SCAs) developed using this process have successfully passed flight qualifications for shock, vibration, temperature cycling and 1,000 hour burn-in, with no failures or degradation.
One of the biggest advantages of using the DBH technique is that these process steps can be performed at the wafer level to improve uniformity, increase yield and decrease cost. An example of a complete hybridized FPA is shown in Figure 5a and a diced example of a larger die is shown in Figure 5b.
The current state for these technologies encompasses a wide range of maturity. The baseline DBH process flow is being exercised on a variety of programs to develop large format digital FPAs for visible and near-IR imaging. In these programs, small volumes of wafer pairs (2–10 per month) are hybridized, packaged and tested. Development of 3D structures is taking a similar path. Development of larger geometries required for high frequency structures, is also progressing though many of the processes are more challenging than those with smaller structures. In addition, processes are being developed where features can be etched into the surfaces before bonding, resulting in embedded cavities that can later be connected via etching for applications such as microfluidic cooling or microelectromechanical systems (MEMs) packaging.
Raytheon is also developing 3D devices that use different substrate materials, such as fused silica, silicon germanium (SiGe), metal alloys and ceramics. These materials place additional constraints on the thermal budget, making that aspect of the process more difficult, but with the potential advantage of enabling the integration of truly novel and highly integrated structures that provide significant size, weight, power and cost benefits for the final system.
1The JEDEC Solid State Technology Council, originally the Joint Electron Device Engineering Council, is a group that develops open standards for the microelectronics industry such as test methods and device interface standards.
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